Writing to and reading from a RAM or a CAM using current drivers and current sensing logic

ABSTRACT

A static memory device that utilizes differential current bit line drivers to write information into the device&#39;s memory cells, and differential current sensing read amplifiers to read information from the cells. The drivers and amplifiers operate using limited differential current. The use of limited differential current, as opposed to voltages, reduces the power consumed by the device and increases the speed of read and write operations.

[0001] This application claims priority from provisional applicationSer. No. 60/303,247, filed Jul. 6, 2001, which is hereby incorporated byreference in its entirety.

FIELD OF THE INVENTION

[0002] The present invention relates generally to memory circuits and,more particularly to a method of and apparatus for writing to andreading from a memory device using current drivers and current sensinglogic.

BACKGROUND OF THE INVENTION

[0003] An essential semiconductor device is semiconductor memory, suchas a random access memory (RAM) device. A RAM allows a memory circuit toexecute both read and write operations on its memory cells. A typicalexample of a RAM device is a static random access memory (SRAM).

[0004] A standard SRAM cell 10 is shown in FIG. 1. The cell 10 consistsof four transistors 14, 16, 18, 20 that form a bistable flip-flop andtwo control or access transistors 12, 22. The access transistors 12, 22have their gate terminals connected to a word select line WS (also knownas a word line). The first access transistor 12 is coupled between afirst bit line DBIT and a first node A. The second access transistor 22is coupled between a second bit line DBIT_N (typically the complement ofthe first bit line DBIT) and a second node B.

[0005] Data is written or stored into the cell 10 with either a highpotential at node A and a low potential at node B, or a low potential atnode A and a high potential at node B. This means that two stable statesare available, which are defined as either a logic “1” or a logic “0”.The configuration of the four transistors 14, 16, 18, 20 (i.e.,flip-flop) is such that the potentials at the two nodes A, B areretained as long as power is supplied to the cell 10. Thus, unlike otherRAM devices (e.g., DRAM), the SRAM cell 10 does not need to beperiodically refreshed to retain its contents.

[0006] The logic state of the SRAM cell 10 is read by sensing thedifferential voltage developed on the bit line pair comprised of the twobit lines DBIT, DBIT_N. When the word line WS is selected, the accesstransistors 12, 22 are turned on, which allows access to the cell's 10contents via the bit lines DBIT, DBIT_N. In most applications, the SRAMcell 10 is embedded in an array of similar cells. The typical array isorganized into a plurality of rows and columns, with rows correspondingto word lines (e.g., WS) and columns corresponding to the bit lines(e.g., DBIT, DBIT_N). To read data stored in the SRAM array, row andcolumn addresses are used to access the desired memory cell (via the WS,DBIT and DBIT_N). That is, a particular address within the SRAM array isaccessed.

[0007] Another form of memory is the content addressable memory (CAM)device. A CAM is a memory device that accelerates any applicationrequiring fast searches of a database, list, or pattern, such as indatabase machines, image or voice recognition, or computer andcommunication networks. CAMs provide benefits over other memory searchalgorithms by simultaneously comparing the desired information (i.e.,data being stored within a given memory location) against the entirelist of pre-stored entries. As a result of their unique searchingalgorithm, CAM devices are frequently employed in network equipment,particularly routers and switches, computer systems and other devicesthat require rapid content searching.

[0008] In order to perform a memory search in the above-identifiedmanner, CAMs are organized differently than other memory devices (e.g.,SRAM). As set forth above, in an SRAM device, during a memory access,the user supplies an address and reads into or gets back the data at thespecified address. In a CAM, however, data is stored in locations in asomewhat random fashion. The locations can be selected by an addressbus, or the data can be written into the first empty memory location.Every location has a pair of status bits that keep track of whether thelocation is storing valid information in it or is empty and availablefor writing.

[0009] Once information is stored in a memory location, it is found bycomparing every bit in memory with data placed in a match detectioncircuit. When the content stored in the CAM memory location does notmatch the data placed in the match detection circuit, the CAM devicereturns a no match indication. When the content stored in the CAM memorylocation matches the data placed in the match detection circuit, the CAMdevice returns a match indication. In addition, the CAM may return theidentification of the address location in which the desired data isstored. Thus, with a CAM, the user supplies the data and gets back theaddress if there is a match found in memory.

[0010]FIG. 2 illustrates a typical CAM cell 30, which for the most partcomprises an SRAM cell 10. The CAM cell 30 is a static memory device andis sometimes referred to as a static CAM cell. Additional transistors32, 34, 36, 38 are used to report the result of the matching functionperformed by the CAM 30. The matching function is performed by anexclusive-NOR operation, so that a match is only indicated if both thestored bit and a corresponding comparand bit (i.e., bit to be searchedfor) have the same state. The four additional transistors 32, 34, 36, 38are used to perform the exclusive NOR (“XNOR”) and match line MLINEdriving operations (discussed below) and will be referred to herein asthe XNOR transistors 32, 34, 36, 38.

[0011] The first XNOR transistor 32 has its gate coupled to thecomplementary match bit line (MBIT_N) and is coupled between the secondXNOR transistor 34 and a ground potential. The second XNOR transistor 34has its gate coupled to the first node A and is coupled between thefirst XNOR transistor 32 and a match line MLINE. The fourth XNORtransistor 38 has its gate coupled to the match bit line (MBIT) and iscoupled between the third XNOR transistor 36 and a ground potential. Thethird XNOR transistor 36 has its gate coupled to the second node B andis coupled between the fourth XNOR transistor 38 and the match lineMLINE. The match bit line MBIT will contain the value of the comparandwhile the complementary match bit line MBIT_N will contain thecomplementary value of the comparand.

[0012] For writing and reading, the CAM cell 30 is operated as an SRAMcell. That is, the differential bit lines DBIT, DBIT_N are used to latchdata into the cell 30 when writing, while the differential on these bitlines are sensed (via sense amplifiers) during reading. For comparing,the match line MLINE is typically precharged to a high potential (e.g.,VDD). The XNOR transistors 32, 34, 36, 38 compare the internally storedstate of the cell 30 to the state of the comparand (via match bit linesMBIT, MBIT_N). If the states do not match, the match line MLINE ispulled down to the ground potential via the XNOR transistors 32, 34, 36,38 to indicate the mismatch. The match line MLINE is fed to an encoderthat determines whether any matches exists, whether more than one matchexists, and which location is considered the highest priority.

[0013] In SRAM and CAM devices, the bit lines DBIT, DBIT_N traverse thewhole depth of the devices. Being long lines, heavily loaded withcapacitance, read and write operations utilizing the bit lines DBIT,DBIT_N take a significant amount of time to complete and consume a largepercentage of the power dissipated in the memory device. It is desirableto increase the speed of read and write operations and reduce the amountof power consumed during the read and write operations performed in SRAMand CAM devices.

SUMMARY OF THE INVENTION

[0014] The present invention provides a static memory device havingreduced power consumption during read and write operations.

[0015] The present invention provides a static memory device havingincreased read and write operation speeds.

[0016] The above and other features and advantages are achieved by astatic memory device that utilizes differential current bit line driversto write information into the device's memory cells, and differentialcurrent sensing read amplifiers to read information from the cells. Thedrivers and amplifiers operate using limited differential current. Theuse of limited differential current, as opposed to voltages, reduces thepower consumed by the device and increases the speed of read and writeoperations.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The foregoing and other advantages and features of the inventionwill become more apparent from the detailed description of exemplaryembodiments provided below with reference to the accompanying drawingsin which:

[0018]FIG. 1 is a circuit diagram illustrating a typical SRAM cell;

[0019]FIG. 2 is a circuit diagram illustrating a typical CAM cell;

[0020]FIG. 3 is a circuit diagram illustrating an SRAM memory device;

[0021]FIG. 4 is a circuit diagram illustrating a CAM memory device;

[0022]FIG. 5 is a circuit diagram illustrating a differential bit linedriver constructed in accordance with an embodiment of the invention;

[0023]FIG. 6 is a circuit diagram illustrating an exemplary currentcontrol loop circuit;

[0024]FIG. 7 is a circuit diagram illustrating a differential currentsensing read amplifier constructed in accordance with an embodiment ofthe invention;

[0025]FIG. 8 is a circuit diagram illustrating another differential bitline driver constructed in accordance with another embodiment of theinvention;

[0026]FIG. 9 is a circuit diagram illustrating another differentialcurrent sensing read amplifier constructed in accordance with anotherembodiment of the invention;

[0027]FIG. 10 is a circuit diagram illustrating another exemplarycurrent control loop circuit;

[0028]FIG. 11 is a block diagram illustrating a processor systemutilizing an SRAM or CAM constructed in accordance with an embodiment ofthe invention; and

[0029]FIG. 12 is a block diagram illustrating a network router utilizinga CAM constructed in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0030] In the following detailed description, reference is made tovarious specific embodiments in which the invention may be practiced.These embodiments are described with sufficient detail to enable thoseskilled in the art to practice the invention, and it is to be understoodthat other embodiments may be employed, and that structural andelectrical changes may be made without departing from the spirit orscope of the present invention.

[0031]FIG. 3 is a circuit diagram illustrating an SRAM memory device 50.The device 50 includes a plurality of bit line drivers 60 ₀ to 60 _(m),SRAM cells 10 and differential receivers 70 ₀ to 70 _(m). The SRAM cells10 are organized as an array of words WORD 0, WORD 1 to WORD n, eachword comprising m bits.

[0032] The first driver 70 ₀ is connected to receive bit 0 of write data0 WRDI₀, and its complement WRDI_N₀, a write pulse WRPLS_N, bit linereference BLREF, two control signals PCC, NCC and a read pulse RDPLS_N.It should be noted that WRDI₀ and WRDI_N₀ do not have to be complements.In certain circumstances, such as when a write operation is completed,it is desirable to have both WRDI₀ and WRDI_N₀ set to a low level.Typically, it is not desirable to have both WRDI₀ and WRDI_N₀ set to ahigh level. Thus, the combination of the WRDI₀ and WRDI_N₀ can havethree states.

[0033] The first driver 70 ₀ uses the input write data WRDI₀, and itscomplement WRDI_N₀, to drive a first bit line 26 ₀ and a second bit line28 ₀. The bit lines 26 ₀, 28 ₀ are connected to an SRAM cell 10 in eacharray of words WORD 0, WORD 1 to WORD n. The other drivers 70 _(m)receive other bits of the write data (e.g., WRDI_(m) and WRDI_N_(m)) anduse the data to drive other first and second bit lines (e.g., 26 _(m)and a 28 _(m)). The other bit lines 26 _(m), 28 _(m) are connected torespective SRAM cells 10 in each array of words WORD 0, WORD 1 to WORDn. Word select lines WORD SELECT 0, WORD SELECT 1 to WORD SELECT n arerespectively connected to each array of words WORD 0, WORD 1 to WORD nso that one of the words may be selected.

[0034] The first differential receiver 70 ₀ is connected to respectivefirst and second bit lines 26 ₀, 28 ₀ and the read pulse RDPLS_N. InFIG. 3, the illustrated receiver 70 ₀ is connected to the bit lines 26₀, 28 ₀ corresponding to bit 0 (and its complement) of all of the arrayof words WORD 0, WORD 1 to WORD n. In operation, the receiver 70 ₀senses the information on the bit lines 26 ₀, 28 ₀ and outputs read dataRDQ₀ and its complement RDQ_N₀.

[0035] Likewise, the other receivers (e.g., 70 _(m)) are connected torespective first and second bit lines (e.g., 26 _(m), 28 _(m)) and theread pulse RDPLS_N. The other receivers (e.g., 70 _(m)) are connected torespective first and second bit lines (e.g., 26 _(m), 28 _(m)) thatcorrespond to respective bits (and their complements) of all of thearray of words WORD 0, WORD 1 to WORD n. The other receivers (e.g., 70_(m)) in the device 50 operate in the same manner as the first receiver70 ₀. The write pulse WRPLS_N, bit line reference BLREF, control signalsPCC, NCC and read pulse RDPLS_N are described below in more detail withreference to FIGS. 5 to 10.

[0036]FIG. 4 is a circuit diagram illustrating a CAM memory device 80.The device 80 is essentially the same as the SRAM device 50 illustratedin FIG. 3. Thus, the device 80 includes a plurality of bit line drivers60 ₀ to 60 _(m) and differential receivers 70 ₀ to 70 _(m). The device80 uses CAM cells 30 in its arrays rather than SRAM Cells. Otherwise,the configuration of the CAM device 80 is the same as the SRAM device50. As explained above with reference to FIG. 2, the CAM cells 30include inputs for match bit lines (MBIT, MBIT_N) and output connectableto a match line (MLINE). These additional inputs and output, however,are irrelevant for the purposes of the present invention.

[0037] Referring to FIGS. 3 and 4, in the SRAM and CAM devices 50, 80,information is read from the respective memory cells 10, 30 via the bitlines 26 ₀, 28 ₀ to 26 _(m), 28 _(m). Similarly, information is writtenin to the respective memory cells 10, 30 of the SRAM and CAM devices 50,80 via the bit lines 26 ₀, 28 ₀ to 26 _(m), 28 _(m). Traditionally, towrite information in to the devices 50, 80, the bit lines 26 ₀, 28 ₀ to26 _(m), 28 _(m) are asserted to the data level and its inverse (e.g.,complement). A word enable line is set high and used to start the writeoperation. When the write operation is complete, the bit lines 26 ₀, 28₀ to 26 _(m), 28 _(m) are set high and the word enable is set low.

[0038] Prior to reading the contents of the respective memory cells 10,30 of the SRAM and CAM devices 50, 80, the bit lines 26 ₀, 28 ₀ to 26_(m), 28 _(m) are precharged to a high state. The precharging of the bitlines 26 ₀, 28 ₀ to 26 _(m), 28 _(m) prevents the alteration of thecells' 10, 30 contents while the cells 10, 30 are being read. The wordenable is set high and the bit line drivers and the bit line drivers 60₀ to 60 _(m) are tri-stated to allow the selected SRAM or CAM cell(s)10, 30 to discharge one of the bit lines 26 ₀, 28 ₀ to 26 _(m), 28 _(m)to a low level.

[0039] The bit lines 26 ₀, 28 ₀ to 26 _(m), 28 _(m) are long andconnected to numerous devices. The bit lines 26 ₀, 28 ₀ to 26 _(m), 28_(m) are usually segmented to allow small drivers 60 ₀ to 60 _(m) todrive them. When all of the segments are combined, however, the bitlines 26 ₀, 28 ₀ to 26 _(m), 28 _(m) traverse the whole depth of thedevice 50, 80 and are heavily loaded with parasitic capacitance. Beinglong lines, heavily loaded with capacitance, read and write operationsutilizing the bit lines 26 ₀, 28 ₀ to 26 _(m), 28 _(m) take asignificant amount of time to complete and consume a large percentage ofthe power dissipated in the memory device.

[0040] Using current instead of voltage in the write and read processesallows these operations to be executed in a shorter period of time. Theywill also use less power. When read and write operations are not beingperformed, the bit lines 26 ₀, 28 ₀ to 26 _(m), 28 _(m) are usually heldat a high level to prevent accidental corruption of the data stored inthe cells 10, 30. It has been discovered that keeping both bit lines ofa bit line pair (e.g., bit lines 26 ₀, 28 ₀) at the same potential,lower than the high potential level, but higher than VDD/2, will preventthe cells 10, 30 from changing their state. Having both bit lines of thebit line pair (e.g. bit lines 26 ₀, 28 ₀) “idle” at a potential slightlyhigher than VDD/2 enables read and write operations to be performedfaster and with lower power consumption.

[0041] For the write operation, if both bit lines of the bit line pair(e.g. bit lines 26 ₀, 28 ₀) idle at about VDD/2, only a smalldifferential voltage change on the bit lines is required to cause thecells 10, 30 to change state (when desired). This differential voltagemay be in the order of 200 millivolts. As will be discussed below withrespect to FIGS. 5 to 10, using opposing currents on the bit lines tocharge and discharge the parasitic capacitance on the lines allows therate and magnitude of the differential voltage change on the bit linesto be tightly controlled. Moreover, restricting the differential voltagechange to a safe level above the required minimum, but not much more,reduces the time required to execute the write operation and lowers thepower consumption in the process.

[0042]FIG. 5 is a circuit diagram illustrating a differential bit linedriver 60 constructed in accordance with an embodiment of the invention.The driver 60 includes a first p-type transistor 102 and a first n-typetransistor 104 configured as a first CMOS driver 103 and a second p-typetransistor 110 and n-type transistor 112 configured as a second CMOSdriver 111. The first CMOS driver 103 is connected to a first data inputDI while the second CMOS driver 111 is connected a second data inputDI_N. Since the driver 60 is a write driver, the data inputs DI, DI_Nrepresent a write data bit. The second CMOS driver 111 drives a firstbit line output BO while the first CMOS driver 103 drives a second bitline output BO_N. The bit line outputs BO, BO_N are connected to the bitlines (e.g., 26 ₀, 28 ₀) that are connected to memory cells 10, 30 asillustrated in FIGS. 3 and 4.

[0043] The two data inputs DI and DI_N are typically complements of eachother when write data is being input, but in certain circumstances, suchas when a write operation is completed, it is desirable to have both DIand DI_N set to a low level. Typically, it is not desirable to have bothDI and DI_N set to a high level. Similarly, the two bit line outputs BOand BO_N are typically complements of each other when data is beingdriven onto the bit lines, but in certain circumstances, such as when awrite operation is completed, it is desirable to have both BO and BO_Nset to the same level, slightly higher than VDD/2.

[0044] The driver 60 includes a three more p-type transistors 106, 108,118 and four more n-type transistors 114, 116, 120, 122. The thirdp-type transistor 106 is connected between a first voltage (e.g., VDD)and the fourth p-type transistor 108 and has its gate connected to afirst control signal PCC. The first control signal PCC is used tocontrol the resistance of the third p-type transistor 106, making thetransistor 106 essentially a variable resistor. The fourth p-typetransistor 108 is connected between the third p-type transistor 106 andthe second p-type transistor 110 (part of the second CMOS driver 111).The fourth p-type transistor 108 is also connected to the first p-typetransistor 102 and has its gate connected to a complementary enablesignal EN_N. The fourth p-type transistor 108 serves a switch activatedby a complementary enable signal EN_N having a low voltage level.

[0045] The fourth n-type transistor 116 is connected between a secondvoltage (e.g., ground) and the third n-type transistor 114 and has itsgate connected to a second control signal NCC. The second control signalNCC is used to control the resistance of the fourth n-type transistor116, making the transistor 116 essentially a variable resistor. Thethird n-type transistor 114 is connected between the fourth n-typetransistor 116 and the second n-type transistor 112 (part of the secondCMOS driver 111). The third n-type transistor 114 is also connected tothe first n-type transistor 104 and has its gate connected to an enablesignal EN. The third n-type transistor 114 serves as an on/off switchactivated by an enable signal EN with a high voltage level.

[0046] The fifth p-type transistor 118 and the fifth and sixth n-typetransistors 120, 122 form a biasing circuit 121 controllable by theequilibration EQ and complementary equilibration EQ_N signals. The fifthp-type transistor 118 is connected between the first voltage and thesecond bit line output BO_N. The fifth p-type transistor 118 has arelatively large resistance that is switched into the driver 60 when thecomplementary equilibration signal EQ_N is at a low voltage level. Thesixth n-type transistor 122 is connected between the second voltage andthe first bit line output BO. The sixth n-type transistor 122 has arelatively large resistance that is switched into the driver 60 when theequilibration signal EQ is at a high voltage level. The fifth n-typetransistor 120 is connected between the first and second bit lineoutputs BO, BO_N. The fifth n-type transistor 120 has a relatively smallresistance that is switched into the driver 60 when the equilibrationsignal EQ is at a high voltage level.

[0047] In operation, the two CMOS drivers 103, 111 will drive thecurrent based on inputs received from the two data inputs DI, DI_N. Theflow of current is controlled by the third and fourth p-type transistors106, 108 and the third and fourth n-type transistors 114, 116. As isexplained below, the fourth p-type transistor 108 and the third n-typetransistor 114 are switches that allow current to pass through them whenactivated. The third p-type transistor 106 and the fourth n-typetransistor 116 are variable resistors that control the amount of currentflowing in the positive and negative directions.

[0048] For example, when the enable signal EN is high, the complementaryenable signal EN_N is low, the fourth n-type transistor 114 and thefourth p-type transistor 108 are switched on. Current can flow throughthe third p-type and fourth n-type transistors 106, 116. The amount ofcurrent depends on the resistance of the third p-type and fourth n-typetransistors 106, 116, which is controlled by the PCC and NCC signals,respectively. By contrast, if the enable signal EN is low, thecomplementary enable signal EN_N is high, the third n-type transistor114 and the fourth p-type transistor 108 are switched off, whichprohibits current flowing through the third and fourth p-typetransistors 106, 108 and the third and fourth n-type transistors 114,116.

[0049] When the enable signal EN and the first data input DI are highand the second data input DI_N is low, current will flow through thethird and fourth p-type transistors 106, 108, and then through thesecond p-type transistor 110 to the first bit line output BO. There willalso be current flowing in the opposite direction from the second bitline output BO_N through the first n-type transistor 104, and thenthrough the third and fourth n-type transistors 114, 116 to the secondvoltage (e.g., ground).

[0050] When the enable signal EN and the second data input DI_N arehigh, and the first data input DI is low, current will flow through thethird and fourth p-type transistors 106, 108, and then through the firstp-type transistor 102 to the second bit line output BO_N. There willalso be current flowing in the opposite direction from the first bitline output BO through the second n-type transistor 112, and thenthrough the third and fourth n-type transistors 114, 116 to the secondvoltage (e.g., ground).

[0051] The enable signal EN and its complement EN_N are used to enablethe writing process. In contrast, the equilibration signal EQ, and itscomplement EQ_N are used both for writing and reading operations.Whenever a write OR a read operation is commanded, the equilibrationsignal EQ, is set low, and it complement EQ_N is set high. Whenever thewrite or read operation is completed, the equilibration signal EQ isturned high, and its complement EQ_N is turned low. Under no conditionare both the enable signal EN, and the equilibration signal EQ,simultaneously high.

[0052] The current flow described above is conditioned upon the biasingcircuit 121 as follows. If the equilibration signal EQ is high, thecomplementary equilibration signal EQ_N is low, the fifth p-type andfifth and sixth n-type transistors 118, 120, 122 will be activated(i.e., “on”), switching in the large resistances of the fifth p-type andsixth n-type transistors 118, 122 and the smaller resistance of thefifth n-type transistor 120. As described above, if the enable signal ENis low, current does not flow through the third and fourth p-typetransistors 106, 108 and the third and fourth n-type transistors 114,116. The bit line outputs BO, BO_N will be shorted together through thesmall resistance of the activated fifth n-type transistor 120, while atthe same time, the larger resistance of the activated fifth p-typetransistor 118 pulls the first bit line output BO to the first voltageand the larger resistance of the activated sixth n-type transistor 122pulls the second bit line output BO_N to the second voltage. Thus, thetwo bit line outputs BO, BO_N are biased to a predetermined voltagesomewhere between VDD and VDD/2. It is desirable to have thepredetermined voltage set to approximately 55% of VDD (i.e., 0.55*VDD).

[0053] Thus, when the driver 60 is not being enabled for a writeoperation, the bit line outputs BO, BO_N are biased to the predeterminedvoltage. The bit line outputs BO, BO_N are also capacitively loaded atthis time. This is referred to as the tri-state output of the driver 60.

[0054] To activate the driver 60, the enable signal EN is set high andthe equilibration signal EQ is set low. Current is pulled through thedriver 60 depending upon the state of the data inputs DI, DI_N (asdescribed above). Complementary source and sink currents appear on thebit line outputs BO, BO_N. The pulled current changes the predeterminedbias voltage by a few hundred millivolts because some of the capacitanceon the bit line outputs BO, BO_N becomes discharged. For example, thevoltage on the first bit line output BO drops a few hundred millivolts,while the voltage on the second bit line output BO_N goes up a fewhundred millivolts so that the lines are now approximately 500millivolts from each other.

[0055] If a selected cell's content is different than the data beingapplied on the bit lines via the outputs BO, BO_N, the opposing currentson the bit line outputs BO, BO_N will cause the cell to change state tomatch the state of the bit line outputs BO, BO_N. The change occursrather quickly because only a small swing on the bit line outputs BO,BO_N occurs.

[0056] Thus, using opposing currents on the bit lines (via the bit lineoutputs BO, BO_N) to charge and discharge the parasitic capacitance onthe lines allows the rate and magnitude of the differential voltagechange on the bit lines to be tightly controlled. Moreover, restrictingthe differential voltage change to a safe level above the requiredminimum, but not much more, reduces the time required to execute thewrite operation and lowers the power consumption in the process.

[0057]FIG. 6 is a circuit diagram illustrating an exemplary currentcontrol loop circuit 150 that can be used to generate the first andsecond control signals PCC, NCC used by the driver 60 illustrated inFIG. 5. The circuit 150 includes two p-type transistors 152, 158, ann-type transistor 160, an operational amplifier (op amp) 154 and aresistor 162. It should be noted that this is merely one example of howthe control signals PCC, NCC can be generated.

[0058] The first p-type transistor 152 is connected between a firstvoltage (e.g., VDD) and an input of the op amp 154. The resistor 162 isconnected between a second voltage (e.g., ground) and the input of theop amp 154 that is connected to the first p-type transistor 152. Thefirst p-type transistor 152 has its gate connected to the gate and drainterminal of the second p-type transistor 158. The second p-typetransistor 158 has its source terminal connected to the first voltage.The drain terminal of the second p-type transistor 158 is connected tothe n-type transistor 160. The n-type transistor 160 has is gateconnected to the output of the op amp 154 and is connected to the secondvoltage.

[0059] The second input of the op amp 154 is connected to a voltagereference VREF. The output of the op amp 154 is the second controlsignal NCC. The first control signal PCC is formed at the intersectionof the connections between the n-type transistor 160 and the secondp-type transistor 158. The first and second control signal PCC, NCC arecontrolled by the looping feedback into the op amp 154 and the dropbetween the second p-type transistor 158 and the n-type transistor 160.The current of the driver 60 is essentially the voltage reference VREFdivided by the resistance of the resistor 162 multiplied by a gainfactor determined by the current loop and the op amp 154.

[0060] The driver 60 illustrated in FIG. 5 biases the bit lines (via bitline outputs BO, BO_N) to the predetermined voltage (somewhere betweenVDD and VDD/2). When a read out from a selected cell is required, thecell is connected to the biased bit lines. The cell has twocomplementary outputs. Whenever one of these outputs is high, the othermust be low. When the cell is connected to the bit lines, the side ofthe cell which is low pulls the current from its respective bit line todischarge it to a low voltage. The other side of the cell draws nocurrent. A special amplifier is used to sense the current difference andconvert it to a logic 1 or 0 voltage level.

[0061]FIG. 7 is a circuit diagram illustrating a differential currentsensing read amplifier 70 constructed in accordance with an embodimentof the invention. The amplifier 70 includes a four n-type transistors202, 208, 214, 220 and six p-type transistors 204, 206, 210, 212, 216,218. The first n-type transistor 202 is coupled between a first memorycell input CIN and a current mirror circuit 205 comprised of the firstand second p-type transistors 204, 206. The second n-type transistor 208is coupled between a second memory cell input CIN_N (which is typicallythe complement of the first memory cell input CIN) and a second currentmirror circuit 215 comprised of the third and fourth p-type transistors210, 216. The gates of the first and second n-type transistors 202, 208are connected to an enable signal EN.

[0062] The fifth p-type transistor 212 is connected between a firstvoltage (e.g., VDD) and the third n-type transistor 214. The thirdn-type transistor is also connected to a second voltage (e.g., ground).The sixth p-type transistor 218 is connected between the first voltageand the fourth n-type transistor 220. The fourth n-type transistor isalso connected to the second voltage. The gate of the fifth p-typetransistor 212 is connected to the gate of the third n-type transistor214, which is also coupled to the connection between the sixth p-typetransistor 218 and the fourth n-type transistor 220. The gate of thesixth p-type transistor 218 is connected to the gate of the fourthn-type transistor 220, which is also coupled to the connection betweenthe fifth p-type transistor 212 and the third n-type transistor 214.This cross-coupling of the transistors 212, 214, 218, 220 forms aflip-flip circuit 225. The outputs of the flip-flop 225 and thus, theamplifier 70, are first and second sense data outputs Q, Q_N.

[0063] In operation, when the enable signal EN is high (e.g., VDD), thefirst n-type and p-type transistors 202, 208 pull in or sense thecurrent from the memory cell inputs CIN, CIN_N. Typically, reading froma cell pulls one of the bit lines high and the other low. Thus, therewill be a difference in the current that flows through the first n-typeand p-type transistors 202, 208. The current mirrors 205, 215 mirrorthis current flowing through the first n-type and p-type transistors202, 208, respectively. This charges the capacitance, and thus thevoltage, on the input of the fourth p-type and third n-type transistors212, 214 or the capacitance, and the voltage, on the input of the sixthp-type and fourth n-type transistors 218, 220. States of the flip-flipcircuit 225 change by charging the capacitance. Since one current islarger than the other, the voltage goes up faster than the other andbecause of the flip-flip circuit 225, one side goes up and the otherside goes down. Thus, a stable state for the first and second sense dataoutputs Q, Q_N is achieved.

[0064]FIG. 8 is a circuit diagram illustrating another differential bitline driver 360 constructed in accordance with another embodiment of theinvention. The another differential bit line driver 360 includes aninput logic circuit 301, a driver circuit 311 and a biasing circuit 331.

[0065] The input logic circuit 301 includes an AND gate 302, two NORgates 304, 306 and an inverter 308. The AND gate 302 has a first inputconnected to receive a read pulse RDPLS_N and a second input connectedto receive a write pulse WRPLS_N. The read pulse RDPLS_N is at a lowlevel when a read operation is in progress. The write pulse WRPLS_N isat a low level when a write operation is in progress. The first NOR gate304 inputs the first data input DI and the second data input DI_N. Sincethe driver 360 is a write driver, the data inputs DI, DI_N represent awrite data input bit and are typically complements of each other whenwrite data is being input. In certain circumstances, such as when awrite operation is completed, or when writing is not desirable during awrite process, it is desirable to have both DI and DI_N set to a lowlevel.

[0066] The output of the NOR gate 304 is used as an input to the secondNOR gate 306. The second NOR gate 306 also inputs the write pulseWRPLS_N. The output of the second NOR gate 306 is used as an input tothe inverter 308 and as an input to the driver circuit 311. The two datainputs DI, DI_N are also used as inputs by the driver circuit 311. Theoutput of the AND gate 302 is used as an input to the biasing circuit331.

[0067] The driver circuit 311 includes two OR gates 310, 312, second andthird AND gates 314, 316, three p-type transistors 318, 322, 324 andthree n-type transistors 320, 326, 328. The first OR gate 310 inputs thefirst data input DI and the output of the first inverter 308. The secondOR gate 312 inputs the second data input DI_N and the output of thefirst inverter 308. The second AND gate 314 inputs the output of thesecond NOR gate 306 and the first data input DI. The third AND gate 316inputs the output of the second NOR gate 306 and the second data inputDI_N.

[0068] The first p-type transistor 322 is connected between a firstvoltage (e.g., VDD) and a connection between the second and third p-typetransistors 318, 324. The first p-type transistor 322 has its gateconnected to the first control signal PCC. The first control signal PCCis used to control the resistance of the first p-type transistor 322,making the transistor 322 essentially a variable resistor. The output ofthe first OR gate 310 is connected to the gate of the second p-typetransistor 318, which is connected between the first n-type transistor320 and the connection between the first and third p-type transistors322, 324. The third p-type transistor 324 is connected between the firstp-type transistor 322 and the second n-type transistor 326. The outputof the second OR gate 312 is connected to the gate of the third p-typetransistor 324. As will become apparent, the second and third p-typetransistors 318, 324 form a differential current switch 319.

[0069] The first n-type transistor 320 has its gate connected to theoutput of the second AND gate 314 and is also connected to theconnection between the second and third n-type transistors 326, 328. Thesecond n-type transistor 326 has its gate connected to the output of thethird AND gate 316 and is also connected between the third n-type andp-type transistors 326, 324. The first and second n-type transistors320, 326 form a differential current switch 321. The third n-typetransistor 328 is also connected between a second voltage (e.g., ground)and the connection of the first and second n-type transistors 320, 326.The third n-type transistor 328 has its gate connected to the secondcontrol signal NCC, which controls the resistance of the third n-typetransistor 328 essentially making it a variable resistor.

[0070] First and second bit line outputs BO, BO_N are output from thedriver circuit 311, which are connected to first and second bit lines,respectively. The first and second bit line outputs BO, BO_N are alsoconnected to the biasing circuit 331. The biasing circuit 331 includes asecond inverter 330, five n-type transistors 332, 334, 338, 339 344 andfour p-type transistors 336, 340, 342, 346. The fourth n-type and p-typetransistors 332, 336 are each connected between the first and second bitline outputs BO, BO_N. The fourth n-type transistor has its gateconnected to the output of the first AND gate 302. The fourth p-typetransistor 336 has its gate connected to the output of the secondinverter 330.

[0071] The output of the first AND gate 302 is also connected to thegate terminals of the fifth and seventh n-type transistors 334, 339. Thefifth n-type transistor 334 is connected between the first bit lineoutput BO and the second voltage (e.g., ground). The fifth p-typetransistor 340 is coupled between the sixth n-type transistor 338 andthe first voltage. The fifth p-type transistor 340 has its gateconnected to the gate of the sixth p-type 342 and its own drainterminal. The sixth p-type transistor 342 is coupled between the firstvoltage and the eighth n-type transistor 344. The seventh p-typetransistor 346 is coupled between the first voltage and the second bitline output BO_N and has its gate connected to the connection betweenthe sixth p-type transistor 342 and the eighth n-type transistor 344.

[0072] The sixth n-type transistor 338 has its gate terminal connectedto the first bit line output BO and is connected between the fifthp-type transistor 340 and the seventh n-type transistor 339. The seventhn-type transistor 339 is connected between the second voltage 339 andthe sixth n-type transistor 338. The eighth n-type transistor 344 hasits gate connected to the bit line reference BLREF. The fifth and sixthp-type transistors 340, 342 and the sixth and eighth n-type transistors338, 344 form a differential amplifier 341. The first bit line output BOand the bit line reference BLREF are the inputs to the differentialamplifier 341.

[0073] The driver 360 of this embodiment operates essentially the sameas the driver 60 illustrated in FIG. 5. However, this driver 360 is animprovement over the driver 60 illustrated in FIG. 5 for the followingreasons. In the driver 60 (FIG. 5), when both data inputs DI, DI_N werelow at the same time, there is a guarantee that there would be nocurrent on the bit line outputs BO, BO_N. In the present embodiment,current can be blocked during the tri-state case because of the inputlogic circuit 301. Specifically, when DI, DI_N are low, the output ofthe first NOR gate 304 goes high causing the output of the second NORgate 306 to go low (meaning no read or write pulse RDPLS_N, WRPLS_N),the outputs of the second and third AND gates 314, 316 go low and theoutputs of the first and second OR gates 310, 312 go high. This causesall of the transistors 318, 324, 320, 326 in the two differentialswitches 319, 321 to turn off, which blocks the current flow.

[0074] In addition, it is desirable for the driver 311 to have thetri-state condition all of the time except when a write operation isoccurring (i.e., when the write pulse WRPLS_N is set to a low level). Itis also desirable to bias the bit lines all of the time except whenthere is a read or write operation (i.e., when one of the read or writepulses RDPLS_N, WRPLS_N is set to a low level). This is accomplished bytying the bit line outputs BO, BO_N to a known reference BLREF that canbe set and controlled as desired (see FIG. 10).

[0075] For example, the two bit line outputs BO, BO_N may be shorted byeither the fourth n-type or p-type transistors 332, 336 depending uponthe output of first AND gate 302 and second inverter 330. When the fifthn-type transistor 334 is activated, it pulls down the first bit lineoutput BO. The differential amplifier 341, which inputs the first bitline output BO and the bit line reference BLREF operates as follows. Ifthe first bit line output BO is lower than the bit line reference BLREF,then current flows through the sixth and seventh n-type transistors 338,339 to ground, which causes the voltage on the gate of the seventhp-type transistor 346 to be lower, rendering the transistor 346 to bemore active. This pulls the second bit line output BO_N up.

[0076] If the output of the first AND gate 302 goes low (i.e., when oneof the read or write pulses RDPLS_N, WRPLS_N is set to a low level), thebiasing circuit 331 must be disconnected. This occurs by turning off thefourth n-type and p-type transistors 332, 336, and the fifth and seventhn-type transistors 334, 339. Thus, the driver 360 exhibits better biascontrol and allows for the selection of biasing to occur based on theread or write pulses RDPLS_N, WRPLS_N.

[0077]FIG. 9 is a circuit diagram illustrating another differentialcurrent sensing read amplifier 470 constructed in accordance withanother embodiment of the invention. The amplifier 470 includes a firstlatch circuit 401 comprised of three inverters 406, 410, 420, an n-typetransistor 416 and seven p-type transistors 402, 404, 408, 412, 414,418, 422. The amplifier 470 also includes a second latch circuit 433comprised of two n-type transistors 430, 432 and two p-type transistors424, 434. Additional n-type transistors 426, 428, 436, 438 are alsoincluded within the amplifier 470.

[0078] The first p-type transistor 402 has its gate connected to itsdrain and the gate of the third p-type transistor 408. The first p-typetransistor 402 is coupled between the first voltage (e.g., VDD) and thesecond p-type transistor 404. The third p-type transistor 408 isconnected between the first voltage and the input to the second inverter410. The second p-type transistor 404 is connected between the firstp-type transistor 402 and a first cell input CIN. The gate of the secondp-type transistor 404 is connected to an enable signal EN. The secondp-type transistor 404 serves as a sensing transistor for sensing thecurrent of the first cell input CIN. The configuration of the first andthird p-type transistors 402, 408 forms a first current mirror circuit403 that mirrors any current flowing through the second p-typetransistor 404.

[0079] The enable signal EN is also used as an input to the firstinverter 406. The output of the first inverter 406 is connected to thegate of the fourth p-type transistor 412, which is connected between theinput and output of the second inverter 410. A fifth p-type transistor414 has its gate connected to the enable EN and is connected between asecond cell input CIN_N and the sixth p-type transistor 418. The sixthp-type transistor 418 is also connected to the first voltage 418 and hasits gate connected to the seventh p-type transistor 422. The seventhp-type transistor 422 is connected between the first voltage and theinput to the third inverter 420. The fifth p-type transistor 414 servesas a sensing transistor for sensing the current of the second cell inputCIN_N. The configuration of the sixth and seventh p-type transistors418, 422 forms a second current mirror circuit 423 that mirrors anycurrent flowing through the fifth p-type transistor 414.

[0080] The first n-type transistor 416 has its gate connected to theenable signal EN and is connected between the outputs of the second andthird inverters 416, 420. The second and third inverters 410, 420, thefourth p-type transistor 412 and the first n-type transistor 416 form aflip-flop circuit 413. Outputs of the flip-flop circuit 413 areconnected to the gates of the second, third and sixth n-type transistors426, 428, 436. The third n-type transistor 438 is connected between thesecond voltage (e.g., ground) and the second n-type transistor 426. Thesecond n-type transistor 426 is connected between the eighth p-typetransistor 424 and the third n-type transistor 426. The sixth n-typetransistor 436 is connected between an output Q_N of the second latch433 and the connection between the second and third n-type transistors426, 428.

[0081] The eighth and ninth p-type transistors 424, 434 and the fourthand fifth n-type transistors 430, 432 are connected in a cross-coupledmanner forming the second latch circuit 433. The outputs of the secondlatch 433 and thus, the amplifier 470, are first and second sense dataoutputs Q, Q_N.

[0082] In operation, when the enable signal EN is high, the second andfifth p-type transistors 404, 414 are off and the fourth p-type andfirst n-type transistors 412, 416 within the flip-flop circuit 413 areturned on. This shorts the two inverters 410, 420 to get the samepotential on both outputs of the flip-flop 413 (i.e., the outputsconnected to the second and sixth n-type transistors 426, 436). When theenable signal EN is low, the second and fifth p-type transistors 404,414 are on and the fourth p-type and first n-type transistors 412, 416within the flip-flop circuit 413 are turned off. The current differencecan be small for a change in the state of the flip-flop 413.

[0083] Also, when the enable signal EN is low, and the output of thefirst inverter 406 is high, the third n-type transistor 428 isactivated, and either the second or sixth n-type transistors 426, 436are on. Current will flow through either the second or sixth n-typetransistor 426, 436. If, for example, the second n-type transistor 426is on, there will be a voltage on the eight p-type transistors 424,which causes the first output Q to go low.

[0084] If the enable signal EN goes high, the third n-type transistor438 turns off, the seventh n-type transistor 438 turns on, whichactivates the fourth and fifth n-type transistors 430, 432 such that thelatch 433 maintains its state. Thus, the output of the latch 433 followsthe changes of the input data when enabled (via EN) and maintains itslast state when not enabled. Thus, the amplifier 470 of the currentembodiment allows for quick changes of the flip-flop circuit 413responsible for converting the sensed current into the correct logic 1or 0 voltage level. The amplifier 470 is also keeps its data stablebetween read operations.

[0085]FIG. 10 is a circuit diagram illustrating an exemplary currentcontrol loop circuit 750 that may be used to generate the controlsignals PREF, NREF and the bit line reference BLREF by the driver 360.The circuit 750 is similar to the circuit 150 illustrated in FIG. 6 withthe exception that additional resistors 166, 168 are provided betweenthe first and second voltages. The resistors 166, 168 form a voltagedivider that generates the bit line reference BREF. A third p-typeresistor 156 is also added to stabilize the generation of the controlsignals PREF, NREF (which is substantially the same as the generation ofthe PCC and NCC signals illustrated in FIG. 5).

[0086]FIG. 11 illustrates an exemplary processing system 900 which mayutilize a memory device 800 constructed in accordance with an embodimentof the present invention. That is, the memory device 800 may be an SRAMor CAM device that utilizes one of the differential current drivers 60,360 illustrated in FIGS. 5 and 8 and one of the differential currentsensing amplifiers 70, 470 illustrated in FIGS. 7 and 9.

[0087] The processing system 900 includes one or more processors 901coupled to a local bus 904. A memory controller 902 and a primary busbridge 903 are also coupled the local bus 904. The processing system 900may include multiple memory controllers 902 and/or multiple primary busbridges 903. The memory controller 902 and the primary bus bridge 903may be integrated as a single device 906.

[0088] The memory controller 902 is also coupled to one or more memorybuses 907. Each memory bus accepts memory components 908 which includeat least one memory device 800 of the present invention. The memorycomponents 908 may be a memory card or a memory module. Examples ofmemory modules include single inline memory modules (SIMMs) and dualinline memory modules (DIMMs). The memory components 908 may include oneor more additional devices 909. For example, in a SIMM or DIMM, theadditional device 909 might be a configuration memory, such as a serialpresence detect (SPD) memory. The memory controller 902 may also becoupled to a cache memory 905. The cache memory 905 may be the onlycache memory in the processing system. Alternatively, other devices, forexample, processors 901 may also include cache memories, which may forma cache hierarchy with cache memory 905. If the processing system 900include peripherals or controllers which are bus masters or whichsupport direct memory access (DMA), the memory controller 902 mayimplement a cache coherency protocol. If the memory controller 902 iscoupled to a plurality of memory buses 907, each memory bus 907 may beoperated in parallel, or different address ranges may be mapped todifferent memory buses 907.

[0089] The primary bus bridge 903 is coupled to at least one peripheralbus 910. Various devices, such as peripherals or additional bus bridgesmay be coupled to the peripheral bus 910. These devices may include astorage controller 911, an miscellaneous I/O device 914, a secondary busbridge 915, a multimedia processor 918, and an legacy device interface920. The primary bus bridge 903 may also coupled to one or more specialpurpose high speed ports 922. In a personal computer, for example, thespecial purpose port might be the Accelerated Graphics Port (AGP), usedto couple a high performance video card to the processing system 900.

[0090] The storage controller 911 couples one or more storage devices913, via a storage bus 912, to the peripheral bus 910. For example, thestorage controller 911 may be a SCSI controller and storage devices 913may be SCSI discs. The I/O device 914 may be any sort of peripheral. Forexample, the I/O device 914 may be an local area network interface, suchas an Ethernet card. The secondary bus bridge may be used to interfaceadditional devices via another bus to the processing system. Forexample, the secondary bus bridge may be an universal serial port (USB)controller used to couple USB devices 917 via to the processing system900. The multimedia processor 918 may be a sound card, a video capturecard, or any other type of media interface, which may also be coupled toone additional devices such as speakers 919. The legacy device interface920 is used to couple legacy devices, for example, older styledkeyboards and mice, to the processing system 900.

[0091] The processing system 900 illustrated in FIG. 11 is only anexemplary processing system with which the invention may be used. WhileFIG. 11 illustrates a processing architecture especially suitable for ageneral purpose computer, such as a personal computer or a workstation,it should be recognized that well known modifications can be made toconfigure the processing system 900 to become more suitable for use in avariety of applications. For example, many electronic devices whichrequire processing may be implemented using a simpler architecture whichrelies on a CPU 901 coupled to memory components 908 and/or memorydevices 800. These electronic devices may include, but are not limitedto audio/video processors and recorders, gaming consoles, digitaltelevision sets, wired or wireless telephones, navigation devices(including system based on the global positioning system (GPS) and/orinertial navigation), and digital cameras and/or recorders. Themodifications may include, for example, elimination of unnecessarycomponents, addition of specialized devices or circuits, and/orintegration of a plurality of devices.

[0092]FIG. 12 is a simplified block diagram of a router 950 as may beused in a communications network, such as, e.g., part of the Internetbackbone. The router 950 contains a plurality of input lines and aplurality of output lines. When data is transmitted from one location toanother, it is sent in a form known as a packet. Oftentimes, prior tothe packet reaching its final destination, that packet is first receivedby a router, or some other device. The router 950 then decodes that partof the data identifying the ultimate destination and decides whichoutput line and what forwarding instructions are required for thepacket.

[0093] Generally, CAMs are very useful in router applications becausehistorical routing information for packets received from a particularsource and going to a particular destination is stored in the CAM of therouter. As a result, when a packet is received by the router 950, therouter already has the forwarding information stored within its CAM.Therefore, only that portion of the packet that identifies the senderand recipient need be decoded in order to perform a search of the CAM toidentify which output line and instructions are required to pass thepacket onto a next node of its journey.

[0094] Still referring to FIG. 12, router 950 contains the added benefitof employing a semiconductor memory chip containing a CAM device 800,such as the CAM devices constructed in accordance with FIGS. 4-10.Therefore, not only does the router benefit from having a CAM but alsobenefits by having a CAM with reduced power consumption and increasedread and write operation speeds.

[0095] While the invention has been described and illustrated withreference to exemplary embodiments, many variations can be made andequivalents substituted without departing from the spirit or scope ofthe invention. Accordingly, the invention is not to be understood asbeing limited by the foregoing description, but is only limited by thescope of the appended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A method writing data into a static memorydevice comprising the steps of: inputting data to be written into amemory cell, the memory cell being connected to first and second bitlines; generating first and second currents in response to the inputdata; and applying the first and second currents onto the bit lines,wherein said first and second currents represent a value of the inputdata or a tri-state condition.
 2. The method of claim 1 furthercomprising the step of biasing the bit lines to a predetermined voltagelevel when a write operation is not being performed.
 3. The method ofclaim 1 further comprising the step of biasing the bit lines to apredetermined voltage level when a read operation or a write operationis not being performed.
 4. The method of claim 2 wherein thepredetermined voltage is smaller than a first voltage used to power thememory device, but more than half of the first voltage.
 5. The method ofclaim 5 wherein the predetermined voltage is approximately fifty-fivepercent of the first voltage.
 6. The method of claim 1, wherein saidgenerating step comprises: switching in first and second adjustableresistive elements; and applying respective first and second voltages tothe first and second first and second adjustable resistive elements. 7.The method of claim 6 further comprising the step of adjusting the firstand second adjustable resistive elements.
 8. A method of reading datafrom a static memory device comprising the steps of: sensing first andsecond currents from respective first and second bit lines connected toa memory cell of the device; converting the sensed first and secondcurrents into a voltage level representing a logical value of a contentof the cell.
 9. The method of claim 8 wherein said sensing stepcomprises: biasing the bit lines to a predetermined voltage; dischargingone of the bit lines based on the content of the memory cell; andsensing the current on the bit lines.
 10. The method of claim 8 whereinsaid sensing step comprises: biasing the bit lines to a predeterminedvoltage; charging one of the bit lines based on the content of thememory cell; and sensing the current on the bit lines.
 11. The method ofclaim 8 further comprising the step of latching the logical value untilthe next read operation is performed on the cell.
 12. A differentialwrite driver for a static memory circuit, said write driver comprising:an input circuit connected to a memory cell via first and second bitlines, said input circuit inputting data to be written into a memorycell; and a current generating circuit connected to said input circuit,said current generating circuit generating first and second currents inresponse to the input data and applying the first and second currentsonto the bit lines, said first and second currents representing a valueof the input data or a tri-state condition.
 13. The write diver of claim12, further comprising a biasing circuit coupled to said bit lines, saidbiasing circuit biasing the bit lines to a predetermined voltage levelwhen a write operation is not being performed.
 14. The write driver ofclaim 13, wherein the predetermined voltage is smaller than a firstvoltage used to power the driver, but more than half of the firstvoltage.
 15. The write driver of claim 14, wherein the predeterminedvoltage is approximately fifty-five percent of the first voltage. 16.The write driver of claim 12 further comprising a biasing circuitcoupled to said bit lines, said biasing circuit biasing the bit lines toa predetermined voltage level when a read operation or a write operationis not being performed.
 17. The write driver of claim 16, wherein thepredetermined voltage is smaller than a first voltage used to power thedriver, but more than half of the first voltage.
 18. The write driver ofclaim 17, wherein the predetermined voltage is approximately fifty-fivepercent of the first voltage.
 19. The write driver of claim 12, whereinsaid generating circuit comprises: a first adjustable resistive elementconnected to a first voltage, a resistance of said first adjustableresistive element being controllable by a first control signal; a secondadjustable resistive element connected to a second voltage, a resistanceof said second adjustable resistive element being controllable by asecond control signal; a first switch for switching in the resistance ofthe first adjustable resistive element in response to a third controlsignal; and a second switch for switching in the resistance of thesecond adjustable resistive element in response to a fourth controlsignal, wherein said first voltage is applied to said first adjustableresistive element and said second voltage is applied to said secondadjustable resistive element when said third and fourth control signalsare received.
 20. The write driver of claim 19, wherein the fourthcontrol signal is a complement of the third control signal.
 21. Thewrite driver of claim 20, wherein said third control signal is an enablesignal and the fourth control signal is a complement of the enablesignal.
 22. The write driver of claim 19 further comprising a currentloop generating circuit for generating the first and second controlsignals based on a reference voltage and a resistance of said currentloop generating circuit.
 23. The write driver of claim 12 wherein saidinput circuit further comprises an input logic circuit for inputting thedata and first and second control signals, wherein said first and secondcontrol signals are used to determine if a read or write operation is inprogress.
 24. The write driver of claim 12, further comprising a biasingcircuit comprising: a first resistive element coupled between a firstvoltage and the first bit line; a second resistive element coupledbetween a second voltage and the second bit line; and a third resistiveelement coupled between the first and second bit lines, wherein saidresistive elements are controlled to produce a predetermined voltagelevel on said bit lines when a write operation is not being performed.25. The write driver of claim 24, wherein said biasing circuit furthercomprises a bit line reference and said bit line reference is used togenerate said predetermined voltage.
 26. A current sensing receivercircuit for a static memory device comprising: a current sensing circuitconnected to first and second bit lines, said current sensing circuitrespectively sensing first and second currents from said first andsecond bit lines, said bit lines being connected to a memory cell of thedevice; and a conversion circuit coupled to said first and secondcurrents, said conversion circuit converting the first and secondcurrents into a voltage level representing a logical value of a contentof the cell.
 27. The current sensing receiver of claim 26 wherein saidconversion circuit comprises a flip-flop circuit.
 28. The currentsensing receiver of claim 27 wherein the flip-flop circuit latches thelogical value until the next read operation is performed on the cell.29. The current sensing receiver of claim 26 wherein said conversioncircuit comprises: a first latching circuit coupled to said first andsecond currents; and a second latching circuit coupled to the output ofsaid first latching circuit) wherein said first latch circuit convertsthe first and second currents into the voltage level representing thelogical value of the content of the cell and said second latchingcircuit maintains the logic value until the next read operation isperformed on the cell.
 30. A memory circuit comprising: a memory cell;an input circuit connected to said memory cell via first and second bitlines, said input circuit inputting data to be written into said memorycell; a current generating circuit connected to said input circuit, saidcurrent generating circuit generating first and second currents inresponse to the input data and applying the first and second currentsonto the bit lines during a write operation, said first and secondcurrents representing a value of the input data or a tri-statecondition; a current sensing circuit connected to the first and secondbit lines, said current sensing circuit respectively sensing third andfourth currents from the first and second bit lines during a readoperation; and a conversion circuit coupled to said third and fourthcurrents, said conversion circuit converting the third and fourthcurrents into a voltage level representing a logical value of a contentof the cell.
 31. A processor system comprising: a processor; a memorycircuit connected to said processor, said memory circuit comprising adifferential write driver for a static memory circuit, said write drivercomprising: an input circuit connected to a memory cell via first andsecond bit lines, said input circuit having first and second inputs forinputting data to be written into said memory cell; and a currentgenerating circuit connected to said first and second inputs, saidcurrent generating circuit generating first and second currents inresponse to the input data and applying the first and second currentsonto the bit lines, said first and second currents representing a valueof the input data or a tri-state condition.
 32. The system of claim 31,wherein said write driver further comprises a biasing circuit coupled tosaid bit lines, said biasing circuit biasing the bit lines to apredetermined voltage level when a write operation is not beingperformed.
 33. The system of claim 32, wherein the predetermined voltageis smaller than a first voltage used to power the driver, but more thanhalf of the first voltage.
 34. The system of claim 32, wherein thepredetermined voltage is approximately fifty-five percent of the firstvoltage.
 35. The system of claim 31, wherein said write driver furthercomprises a biasing circuit coupled to said bit lines, said biasingcircuit biasing the bit lines to a predetermined voltage level when aread operation or a write operation is not being performed.
 36. Thesystem of claim 35, wherein the predetermined voltage is smaller than afirst voltage used to power the driver, but more than half of the firstvoltage.
 37. The system of claim 35, wherein the predetermined voltageis approximately fifty-five percent of the first voltage.
 38. The systemof claim 31, wherein said generating circuit comprises: a firstadjustable resistive element connected to a first voltage, a resistanceof said first adjustable resistive element being controllable by a firstcontrol signal; a second adjustable resistive element connected to asecond voltage, a resistance of said second adjustable resistive elementbeing controllable by a second control signal; a first switch forswitching in the resistance of the first adjustable resistive element inresponse to a third control signal; and a second switch for switching inthe resistance of the second adjustable resistive element in response toa fourth control signal, wherein said first voltage is applied to saidfirst adjustable resistive element and said second voltage is applied tosaid second adjustable resistive element when said third and fourthcontrol signals are received.
 39. The system of claim 38, wherein thefourth control signal is a complement of the third control signal. 40.The system of claim 38, wherein said third control signal is an enablesignal and the fourth control signal is a complement of the enablesignal.
 41. The system of claim 38, wherein said write driver furthercomprises a current loop generating circuit for generating the first andsecond control signals based on a reference voltage and a resistance ofsaid current loop generating circuit.
 42. The system of claim 31 whereinsaid input circuit further comprises an input logic circuit forinputting the data and first and second control signals, wherein saidfirst and second control signals are used to determine if a read orwrite operation is in progress.
 43. The system of claim 31, wherein saidwrite driver further comprises a biasing circuit comprising: a firstresistive element coupled between a first voltage and the first bitline; a second resistive element coupled between a second voltage andthe second bit line; and a third resistive element coupled between thefirst and second bit lines, wherein said resistive elements arecontrolled to produce a predetermined voltage level on said bit lineswhen a write operation is not being performed.
 44. The system of claim43, wherein said biasing circuit further comprises a bit line referenceand said bit line reference is used to generate said predeterminedvoltage.
 45. A processor system, comprising: a processor; and a memorycircuit connected to said processor, said memory circuit comprising acurrent sensing receiver circuit for a static memory device comprising:a current sensing circuit connected to first and second bit lines, saidcurrent sensing circuit respectively sensing first and second currentsfrom said first and second bit lines, said bit lines being connected toa memory cell of the device; and a conversion circuit coupled to saidfirst and second currents, said conversion circuit converting the firstand second currents into a voltage level representing a logical value ofa content of the cell.
 46. The system of claim 45 wherein saidconversion circuit comprises a flip-flop circuit.
 47. The system ofclaim 46 wherein the flip-flop circuit latches the logical value untilthe next read operation is performed on the cell.
 48. The system ofclaim 45 wherein said conversion circuit comprises: a first latchingcircuit coupled to said first and second currents; and a second latchingcircuit coupled to the output of said first latching circuit, whereinsaid first latch circuit converts the first and second currents into thevoltage level representing the logical value of the content of the celland said second latching circuit maintains the logic value until thenext read operation is performed on the cell.
 49. A memory circuitcomprising: a static memory cell connected to first and second bitlines; an input circuit, said input circuit having first and secondinputs, said inputs corresponding inputting data to be written into amemory cell; and a current generating circuit connected to said inputcircuit, said current generating circuit generating first and secondcurrents in response to the input data and applying the first and secondcurrents onto the bit lines, said first and second currents representinga value of the input data or a tri-state condition.
 50. The memorycircuit of claim 49, further comprising a biasing circuit coupled tosaid bit lines, said biasing circuit biasing the bit lines to apredetermined voltage level when a write operation is not beingperformed.
 51. The memory circuit of claim 49, further comprising abiasing circuit coupled to said bit lines, said biasing circuit biasingthe bit lines to a predetermined voltage level when a read operation ora write operation is not being performed.
 52. The memory circuit ofclaim 51, wherein the predetermined voltage is smaller than a firstvoltage used to power the driver, but more than half of the firstvoltage.
 53. The memory circuit of claim 49, wherein said generatingcircuit comprises: a first adjustable resistive element connected to afirst voltage, a resistance of said first adjustable resistive elementbeing controllable by a first control signal; a second adjustableresistive element connected to a second voltage, a resistance of saidsecond adjustable resistive element being controllable by a secondcontrol signal; a first switch for switching in the resistance of thefirst adjustable resistive element in response to a third controlsignal; and a second switch for switching in the resistance of thesecond adjustable resistive element in response to a fourth controlsignal, wherein said first voltage is applied to said first adjustableresistive element and said second voltage is applied to said secondadjustable resistive element when said third and fourth control signalsare received.
 54. The memory circuit of claim 53, further comprising acurrent loop generating circuit for generating the first and secondcontrol signals based on a reference voltage and a resistance of saidcurrent loop generating circuit.
 55. The memory circuit of claim 49,wherein said input circuit further comprises an input logic circuit forinputting the data and first and second control signals, wherein saidfirst and second control signals are used to determine if a read orwrite operation is in progress.
 56. The memory circuit of claim 49,further comprising a biasing circuit comprising: a first resistiveelement coupled between a first voltage and the first bit line; a secondresistive element coupled between a second voltage and the second bitline; and a third resistive element coupled between the first and secondbit lines, wherein said resistive elements are controlled to produce apredetermined voltage level on said bit lines when a write operation isnot being performed.
 57. The memory circuit of claim 49, wherein thememory cell is a static random access memory cell.
 58. The memorycircuit of claim 49, wherein the memory cell is a content addressablememory cell.
 59. A memory circuit comprising: a static memory cellconnected to first and second bit lines; a current sensing circuitconnected to said first and second bit lines, said current sensingcircuit respectively sensing first and second currents from said firstand second bit lines; and a conversion circuit coupled to said first andsecond currents, said conversion circuit converting the first and secondcurrents into a voltage level representing a logical value of a contentof said cell.
 60. The memory circuit of claim 59, wherein saidconversion circuit comprises a flip-flop circuit that latches thelogical value until the next read operation is performed on the cell.61. The memory circuit of claim 59, wherein said conversion circuitcomprises: a first latching circuit coupled to said first and secondcurrents; and a second latching circuit coupled to the output of saidfirst latching circuit, wherein said first latch circuit converts thefirst and second currents into the voltage level representing thelogical value of the content of the cell and said second latchingcircuit maintains the logic value until the next read operation isperformed on the cell.
 62. A network router comprising: a processor; anda content addressable memory device connected to said processor, saidcontent addressable memory comprising: a content addressable memorycell; an input circuit connected to input data to be written into saidmemory cell; a current generating circuit connected to said inputcircuit, said current generating circuit generating first and secondcurrents in response to the input data and applying the first and secondcurrents onto the bit lines during a write operation, said first andsecond currents representing a value of the input data or a tri-statecondition; a current sensing circuit connected to the first and secondbit lines, said current sensing circuit respectively sensing third andfourth currents from the first and second bit lines during a readoperation; and a conversion circuit coupled to said third and fourthcurrents, said conversion circuit converting the third and fourthcurrents into a voltage level representing a logical value of a contentof the cell.